1. Field of the Invention
This patent relates generally to the field of electrical characterization of materials and structures and, more particularly, to a non-destructive testing device and method for characterization of semiconductor materials using combined C-V and I-V testing using atomic force probing. It also pertains to the use of multiple probes on a semiconductor device at the nanoscale in order to enable new, novel combinations of measurements of current, charge, and capacitance.
2. Description of the Related Art
It is well known that in the processing and fabrication of semiconductor structures, it is advantageous to measure their performance and properties as early as possible. Furthermore is also well known that parameters such as impurity density and dielectric properties are critical in modern semiconductor devices. The ability to measure these properties on real devices dimensions on the nanoscale is also of great benefit.
There are many methods for accomplishing these measurements. One of these methods for measuring device properties is Capacitance Voltage spectroscopy or CV. Another common measurement is Current Voltage spectroscopy or IV. IV spectroscopy is accomplished by biasing one or more nodes of a structure and measuring the resulting current flow into those nodes. IV is used to great effect in all levels of device characterization and there are a multitude of instruments design to measure current called source-measurement units or SMU's. Measurements in the range from fempto-amps (fA) to milli-amps are useful. To reach the smallest fA current levels, special techniques of guarding and shielding are required while careful attention needs to be paid to leakage currents and interference from noise sources.
Typically instrumentation for measuring CV requires sufficient size of the capacitor plates such that the measured capacitance is on the order of 10's to 100's of picofarads. The structures must be of a size to provide this much capacitance as shown in the basic Capacitance equation:C=εA/T 
Where T is the spacing between the plates, A the area of the plates and s the dielectric constant of the insulator material between the plates. For Semiconductor and electronic materials the material to be measured usually will include the semiconductor as one of the plates and either poly silicon or metal as the second though certainly it is understood that simple material substitution is implied in this disclosure and that constructions other than the parallel metal oxide silicon structure referred to at present arc not beyond the scope of this disclosure. For a structure with a very thin 5 nanometer nitrided oxide insulator and a maximum capacitance of 10 picofarads, the implied size of a square plate would be about 375 μm on a side. The standard method for measuring such a capacitance is to deposit a plate of this area onto a dielectric and then connect a probe to a pad of this size. It is undesirable to construct such test structures on wafers thereby effectively sacrificing them. Furthermore, the deposition process may adversely affect the properties of the device to be measured and therefore make enable the desired measurement.
One method to overcome the requirement of sacrificing wafers or affecting the properties of the device under test is to incorporate the test structure into the normal process of the wafer. Though effective and of great value in detecting the properties, test structures are typically only available for measurement after full processing of the wafer is complete. Furthermore, if local properties of a length scale on the order of much less than the 10 picofarad structure discussed above, then it is advantageous to have a method where the area required for the measurement is a few microns or less. In this case, the capacitance measured will be on the order of fempto farads to atto farads, a reduction of 3 to 6 orders of magnitude.
The present invention is directed at enabling measurement of electrical properties without the required construction of probing pads or the need to wait for complete processing of test structures in order to record said performance. The signal to noise ratio of the measurement is adversely affected by reduction of the sampled area. It is the subject of the present invention to employ novel probe design, novel instruments design, and novel combinations of measurement results in order to overcome the orders of magnitude reduction of signal resulting from the smaller sampled area.